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-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/12/2007
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.all;

ENTITY g_inv32 IS
	PORT (	input			: IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
      		q	 			: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
			);
END g_inv32;

ARCHITECTURE behav OF g_inv32 IS
BEGIN
	q(0) <= NOT input(0);
	q(1) <= NOT input(1);
	q(2) <= NOT input(2);
	q(3) <= NOT input(3);
	q(4) <= NOT input(4);
	q(5) <= NOT input(5);
	q(6) <= NOT input(6);
	q(7) <= NOT input(7);
	q(8) <= NOT input(8);
	q(9) <= NOT input(9);
	q(10) <= NOT input(10);
	q(11) <= NOT input(11);
	q(12) <= NOT input(12);
	q(13) <= NOT input(13);
	q(14) <= NOT input(14);
	q(15) <= NOT input(15);
	q(16) <= NOT input(16);
	q(17) <= NOT input(17);
	q(18) <= NOT input(18);
	q(19) <= NOT input(19);
	q(20) <= NOT input(20);
	q(21) <= NOT input(21);
	q(22) <= NOT input(22);
	q(23) <= NOT input(23);
	q(24) <= NOT input(24);
	q(25) <= NOT input(25);
	q(26) <= NOT input(26);
	q(27) <= NOT input(27);
	q(28) <= NOT input(28);
	q(29) <= NOT input(29);
	q(30) <= NOT input(30);
	q(31) <= NOT input(31);
END behav;